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JEET, Vol. 13, No. 1, January 2018
FPGA Implementation of Diode Clamped Multilevel Inverter for Speed Control of Induction Motor
C.L. Kuppuswamy
Area B - Electric Machinery and Power Electronics
Abstract This work proposes FPGA implementation of Carrier Disposition PWM for closed loop seven level diode clamped multilevel inverter in speed control of induction motor. VLSI architecture for carrier Disposition have been introduced through which PWM signals are fed to the neutral point seven level diode clamped multilevel using which the speed of the induction motor is controlled. This proposed VLSI architecture makes the power circuit to work better with reduced stresses across the switches and a very low voltage and current total harmonic distortion (THD). The output voltages, currents, torque & speed characteristics for seven level neutral point diode clamped multilevel inverter for AC drive was studied. It has observed the proposed scheme introduces less distortion and harmonics. The results were validated using real time results.
Keyword VLSI Architecture for PD carrier PWM,FPGA,Diode clamped MLI,Total Harmonic distortion
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