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JEET, Vol. 12, No. 5, September 2017
Compact Current Model of Single-Gate/Double-Gate Tunneling Field-Effect Transistors
Yun Seop Yu
Area C - Electrophysics and Applications
Abstract A compact current model applicable to both single-gate (SG) and double-gate (DG) tunneling field-effect transistors (TFETs) is presented. The model is based on Kanes band-to-band tunneling (BTBT) model. In this model, the well-known and previously-reported quasi-2-D solution of Poissons equation is used for the surface potential and length of the tunneling path in the tunneling region. An analytical tunneling current expression is derived from expressions of derivatives of local electric field and surface potential with respect to tunneling direction. The previously reported correction factor with three fitting parameters, compensating for superlinear onset and saturation current with drain voltage, is used. Simulation results of the proposed TFET model are compared with those from a technology computer-aided-design (TCAD) simulator, and good agreement in all operational bias is demonstrated. The proposed SG/DG-TFET model is developed with Verilog-A for circuit simulation. A TFET inverter is simulated with the Verilog-A SG/DG-TFET model in the circuit simulator; the model exhibits typical inverter characteristics, thereby confirming its effectiveness.
Keyword Compact model,Band-to-band tunneling (BTBT),Surface potential,Tunneling fieldeffect- transistor (TFET)
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